Space Industry Is Standardizing on RISC-V

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BOLOGNA, Italy — At the RISC-V Summit Europe 2026, semiconductor designers, software developers, and aerospace engineers gathered to discuss the changing landscape of computing in space.

During the “RISC-V in Space” session on June 10, experts from the European Space Agency, NASA’s Jet Propulsion Laboratory, Microchip, and Frontgrade Gaisler explained how quickly the open-standard instruction set is being adopted for space missions.

RISC-V in Space panel (Source: EE Times | Pablo Valerio)History of space semiconductors

Space exploration and computing have always been closely linked. Gianluca Furano from the European Space Agency said that today’s embedded systems actually started in space, shaped by the tough demands of early missions such as Voyager. Since space is so harsh, engineers have always looked for reliable, open-standard designs that they can check and adapt.

About thirty years ago, the European Space Agency chose SPARC (Scalable Processor ARChitecture) as its main instruction set because it was open and had well-developed tools.

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In an exclusive interview during the summit, Sandi Habinc, general manager of Swedish aerospace semiconductor firm Frontgrade Gaisler, discussed the evolution of space-grade processors and the industry’s move toward RISC-V in both the commercial and government sectors.

Frontgrade Gaisler’s roots are tied directly to this era. “We are a spinoff from the European Space Agency [established] 25 years ago,” Habinc told EE Times. He noted that its co-founder, Jiri Gaisler, previously developed SPARC processors for the International Space Station. In 1997, Gaisler received a fellowship to develop an independent VHDL model of a SPARC processor for space applications, which became known as the LEON processor.

“It was the first VHDL advanced chip, and we put that in open source as the European Space Agency,” Habinc said. The LEON processor became a standard component in the European aerospace industry, fostering a collaborative ecosystem in which multiple vendors could manufacture chips based on the same core IP.

Shift from legacy to RISC-V

Even though SPARC was successful in Europe and PowerPC in the U.S., the aerospace industry is undergoing a hardware change. Fewer engineers are familiar with these legacy systems, and updating them to meet modern requirements is costly.

Habinc explained the financial and technical rationale for adopting RISC-V. “SPARC is going to be used forever, right, because if you use something in space once, you will always use it,” Habinc said. “But we had a 32-bit machine. To go to 64, it was a huge investment for us.”

By transitioning to RISC-V, the company bypassed many development hurdles. “To do that on RISC-V, it came free of charge,” Habinc noted, referencing the readily available open-standard foundations of the RISC-V 64-bit architecture.

Another reason for this change is the need to reduce technical debt. In his talk, Furano said that reliance on old technology has slowed down traditional microprocessors, describing these old systems as “ballast in space”. RISC-V lets engineers remove outdated parts and tailor processors to the tight size, weight, and power limits of space missions, as well as for emerging uses such as neural networks.

Bridging the architecture gap

To help customers move from older systems, Frontgrade Gaisler created a processor that supports both architectures. Its new RISC-V processor line is called NOEL, which is “LEON” spelled backward, showing the change from big-endian to little-endian memory. It has a similar internal design to the earlier version.

The company said it is preparing to launch the GR765, an eight-core processor designed to withstand radiation. It includes both SPARC and RISC-V pipelines. “You can choose at boot to run it in SPARC or in RISC-V mode,” Habinc said. “At the same time, we have all the legacy support. It’s backward compatible with all the code people have ever written.”

Habinc continued, “A company that’s already using the old ones can easily just start using our chip. In the future, when they don’t find spark engineers because they don’t grow on trees, without changing the board or the box, they can just switch the software.”

A key part of this approach is keeping the ecosystem open and avoiding restrictive licenses. Frontgrade Gaisler sells its fault-tolerant technology but also releases basic processor code as open source. “We make sure that everything we do is RISC-V compatible,” Habinc said. “We have zero vendor lock-in. If you work with us now and you find another supplier in the future, we’re not there to prevent you.”

Next era of flight computing at NASA

RISC-V is also widely adopted in the U.S. In 2022, Microchip received a NASA contract to build the high-performance spaceflight computing processor (HPSC) for the next generation of space missions. Ted Speers, a technical fellow at Microchip, said the new PIC64-HPSC is a processor with eight SiFive RISC-V cores with modern features such as Ethernet and PCI Express.

(Source: Microchip)

Théa-Martine Gauthier, a project architect at NASA’s Jet Propulsion Laboratory, stressed the importance of this new hardware. “We love our [SPARC-based] RAD750s so much we fly them all the time,” Gauthier said. “Still, we need to advance the general-purpose compute.” Deep space missions need more autonomy so they can process data on board instead of sending everything back to Earth over slow connections.

The new HPSC combines high-performance computing, a 240-gigabit network switch, and robust cybersecurity into a single, reliable system. Gauthier emphasized the importance of using an open instruction set.

“PIC64-HPSC is completely designed around open standards,” she said. She added that RISC-V will help science missions lower costs and speed up the delivery of valuable data.

Commercial space and the hypercomputing continuum

Commercial space companies are also quickly adopting these technologies. The session discussed the “Hypercomputing Continuum,” which aims to combine supercomputing, cloud computing, and edge computing in space.

Microchip’s Speers discussed the rapid growth of the space economy, especially in satellite networks, defense, and exploration. He predicted that most tech companies would soon develop space strategies, citing initiatives such as Google’s Project Suncatcher and SpaceX’s plans for orbital data centers.

Habinc elaborated on the role of commercial space companies, especially SpaceX. “SpaceX is lifting everything,” he said. He explained that these firms are cutting launch costs and launching large networks for communication and computing. “They’re gonna build their own data centers [and] AI in space, that’s the only way forward,” Habinc said. He also pointed out that SpaceX makes everything from the chips to the final services.

Also, telecom infrastructure is moving into space. In Europe, the IRIS² project is working to create a secure satellite network for both government and business use. Frontgrade Gaisler is developing 7-nm RISC-V chips to help build this network.

Habinc also predicted that future 6G networks will rely more on space-based hardware rather than ground cell towers. “Cell towers that are not really resilient on the ground can be killed,” Habinc said. “They will be moved more and more in space.”

By working together across continents and following open standards, the aerospace semiconductor industry is changing its core technologies. Standardizing on RISC-V helps organizations ensure their hardware lasts and adapts to the fast-growing space economy.