NASA is on the verge of a major technological revolution ahead of even more ambitious interplanetary missions. In partnership with Microchip Technology, the space agency has begun extensive testing of a next-generation processor. This chip is designed to address one of the biggest challenges facing modern space exploration: the lack of onboard computing power. Thanks to this innovation, future spacecraft will be able to independently analyze data and make critical decisions in real time, without waiting for a signal to travel millions of kilometers to Earth and back.
High-Performance Spaceflight Computing SoC. Source: NASA/Ryan Lannom
Engineers are confident that this leap in performance will transform the approach to exploring deep space, safely landing on other planets, and carrying out ambitious crewed missions to the Moon and Mars.
Space radiation vs. modern technology
Interesting fact: The phone or laptop you’re using to read this article has a processor hundreds of times more powerful than the ones used in spacecraft or rovers. Is NASA really cutting corners on hardware? Actually, the answer lies in the harsh space environment.
Modern missions are often forced to rely on very outdated chips, which are, however, extremely reliable because they have stood the test of time. For example, the Perseverance and Curiosity rovers incorporate modified RAD750 processors, which are a radiation-hardened version of the PowerPC 750—a chip used in Apple iMac G3 computers and iBook G3 laptops from 1998 to 2005.
Although modern commercial electronics are powerful, they are not capable of withstanding the barrage of high-energy particles emitted by the Sun and galactic cosmic rays. Radiation instantly damages the delicate transistors in modern processors, causing malfunctions that force systems to enter “safe mode” and shut down scientific instruments. Because of these limitations, the spacecraft are merely data collectors—they gather data and send it back to Earth, where powerful servers do all the “heavy lifting” for them. NASA’s new processor is designed to permanently eliminate this “bottleneck,” as it is known in engineering.
HPSC Project
The new device is at the heart of NASA’s High-Performance Spaceflight Computing (HPSC) program. Preliminary tests conducted at the renowned Jet Propulsion Laboratory (JPL) in California have yielded impressive results: the new processor is nearly 500 times more efficient than current radiation-resistant counterparts.
SoC High Performance Spaceflight Computing. Source: NASA/Ryan Lannom
Technologically, the processor is designed as an SoC (System on a Chip). This means that instead of a set of separate boards, the central processing units, network communications, memory, and I/O interfaces are integrated into a single, extremely compact unit. In essence, its architecture closely resembles the design of chips used in standard tablets or smartphones. However, the “space-grade” version offers an unprecedented level of protection against radiation, vibrations, and extreme temperature fluctuations.
Key Technical Specifications of the SoC HPSC
Architecture: 64-bit RISC-V SoC with 8 cores (two clusters of 4 SiFive X280 cores each). Clock speed: up to 500 MHz.
Vector Computing: Support for the RISC-V Vector Extension (RVV) with a 512-bit register width and scalability up to 4096 bits.
Performance: Over 100 times more efficient per watt than NASA’s current space processors.
Memory: two DDR4 ports with a bandwidth of 51.2 GB/s.
Networking: Built-in 240 Gbps TSN Ethernet switch with RDMA (RoCEv2), enabling the development of spacecraft with Ethernet connectivity.
On-board AI: Optimized for neural networks, CNNs, TensorFlow, and OpenXLA—meaning it can perform machine learning directly in space.
Protection: RHBD, multi-level fault tolerance, Dual-Core Lockstep, ECC memory, fault-tolerant system controller.
Energy efficiency: over 70 power islands, deep sleep modes, Power Dial for fine-tuned power management.
Extreme crash tests in simulated space conditions
To get the green light for flight, the chip has to go through a grueling series of tests in the lab. A JPL team led by Jim Butler has been testing the processor for months under conditions that meticulously simulate deep space.
The equipment is subjected to intense radiation, frozen and heated to extreme temperatures, tested for resistance to severe vibrations during launch, and evaluated for susceptibility to electromagnetic interference. Engineers pay particular attention to testing the landing algorithms. Using high-precision simulations based on data from previous real-world NASA missions, scientists are testing whether the chip can instantly process the flood of data coming in from landing sensors and radars.
Artificial intelligence on board
The primary goal of this project is to enable the use of artificial intelligence directly in space. With this level of computing power, future probes and rovers will be able to analyze terrain in real time, plot safe routes on their own, avoid hazards, and instantly adapt to unpredictable environmental conditions without needing to seek permission from mission control on Earth.
Microchip Technology, which has been the project’s primary commercial partner since 2022, has invested its own resources in the development. Once the chip receives final certification, it will serve as the “brain” of a new generation of rovers, orbital stations, deep-space probes, and crewed bases for astronauts. Moreover, the exceptional reliability of these processors will inevitably find applications on Earth as well—the technology has the potential to significantly enhance the safety of control systems in aviation and modern automotive engineering.
We previously discussed how Google Willow quantum processor performs computations in parallel universes.
According to NASA